A wide variety of data serializer architectures are utilized in various high speed serial applications including video, telecommunications, recording and others. As the speed requirements that must be met by data serializers have increased, the corresponding serializer architectures have likewise increased in complexity. Such complexities typically include the use of a serial buffer memory for the temporary storage of data apart from a main buffer memory. Use of a serial data buffer memory allows the sourcing of serial data to or from the data serializer substantially independent of any memory access activity directed to the main buffer memory by a host processor. Data is transferred between the serial and main buffer memories periodically in a parallel data "burst" within a parallel data load cycle.
Although a data serializer is typically closely coupled to its serial data buffer memory, a critical performance limitation is the delay from the initiation of a data load cycle transferring new data to the serial buffer memory and the subsequent realization of the first of this new data at the serial output of the data serializer. In typical applications, this delay would define the maximum frequency that serial data can be uniformly sourced by the data serializer or, alternately, the refresh delay period between high frequency data bursts. In either case, it is naturally desirable to decrease this data load cycle initiation to first new data availability delay.
A number of exemplary data serializers are shown in and described in "High Speed, Ram Based Data Serializers", allowed U.S. patent application Ser. No. 805,164, filed Dec. 4, 1985 and assigned to the assignee of the present application. In particular, a dual data line serializer is shown and described. In order to increase the rate that data is sourced from the data serializer, parallel data channels are utilized to obtain respective data from a serial data buffer memory for sourcing during alternate source clock cycles. This effectively allows each data channel two source clock cycles to obtain and present a respective data for sourcing from the serializer. Consequently, a peak data source frequency of approximately twice that of more conventional data serializers is realized.
Unfortunately, each data channel of the dual data line serializer includes a number of sequentially operating address and data stages. Consequently, in a data load cycle providing new data to the serial data buffer memory, the delay to first new data available period is effectively extended by about two additional source clock cycles in order to fully load both serial data channels of the dual data line serializer. If further parallel data channels are utilized, additional clock cycle equivalents to the transfer delay period would likely be required.